The present invention relates to a level shift circuit for use in communicating, without potential insulation, on/off signals from a circuit connected to a common potential such as a ground to a control electrode of a controllable semiconductor device such as a semiconductor switching device on an upper arm of a power-inverting bridge circuit, for example, in a PWM inverter or a switching power supply, the controllable semiconductor device having an electrode (an emitter or a source) that acts as a potential reference for an input control drive signal and that has a potential varying relative to the common potential. Desirably, the present invention relates to a level shift circuit for use in the form of an HVIC (high-voltage IC).
In the interest of cost reduction, level shift circuits free from potential insulation provided be a transformer or a photocoupler have recently been used as circuits for turning on and off a semiconductor switching device constituting an upper arm of a power-inverting (i.e., conversion of a direct current into an alternate current) bridge circuit such as a PWM inverter.
FIG. 7 shows an example configuration of a conventional level shift circuit of this kind. In this FIG., 17 and 18 are output IGBTs connected in series between a main DC power supply Vdc (a positive-electrode side) for a high voltage, for example, 400 V and a common potential COM located at a negative-electrode side of this power supply, in order to form, for example, one phase of a power-inverting bridge circuit of a PWM inverter.
OUT denotes a connection point between an emitter of the upper-arm IGBT 17 of the bridge circuit and the lower-arm IGBT 18 thereof; that is, this is an output terminal for AC power generated by alternately turning on and off the IGBTs 17 and 18.
E2 denotes, for example, a 15-V auxiliary DC power supply (also referred to as a xe2x80x9cdriver power supplyxe2x80x9d) having a negative electrode connected to the common potential COM, and 20 is a driver for turning on and off the lower-arm IGBT 18 and which operates under the auxiliary DC power supply E2.
The remaining part of the circuit constitutes a level shift circuit for driving the upper-arm IGBT 17 of the bridge circuit. That is, reference numeral 1 designates a high-voltage MOSFET for inputting and conducting an on signal 25 consisting of pulses generated by a circuit (not shown) so that the resulting voltage drop in a load resistor 3 is used as a signal to turn on the IGBT 17. Reference numeral 2 designates a high-voltage MOSFET for inputting and conducting an off signal 26 consisting of pulses generated by a circuit (not shown) so that the resulting voltage drop in a load resistor 4 is used as a signal to turn off the IGBT 17.
Normally, the high-voltage MOSFETs 1 and 2 are configured to be equal to each other, as are the load resistors 3 and 4. Constant-voltage diodes 5, 6 connected in parallel to the load resistors 3, 4, respectively, limit any excessive voltage drop in the load resistors 3, 4 to protect NOT circuits 8, 9 or the like, which will be described below.
In the level shift circuit, the two MOSFETs 1 and 2 constitute a circuit section for inputting a signal based on the stationary common potential COM. On the other hand, the portion of the circuit enclosed by the broken line in the figure indicates a circuit section with a varying potential which operates based on the potential of the AC output terminal OUT that alternately follows the common potential COM and the potential Vdc of the main DC power supply depending on whether the IGBTs 17, 18 are turned on or off.
E1 in the circuit enclosed by the broken line denotes, for example, a 15-V auxiliary DC power supply (also referred to as a xe2x80x9cdriver power supplyxe2x80x9d) having a positive electrode connected to a line Vcc1 and a negative electrode connected to the AC output terminal OUT. The NOT circuits 8, 9 and subsequent circuits [consisting of low-pass filter circuits (also simply referred to as xe2x80x9cLPFsxe2x80x9d) 30, 31, a RS flip flop (a RS latch also simply referred to as an xe2x80x9cRS-FFxe2x80x9d) 15, a driver 16, etc.] operate using the auxiliary DC power supply E1 as a power supply.
However, a power supply voltage for a load resistor circuit for the high-voltage MOSFETs 1 and 2 which comprises the load resistors 3, 4 with their upper ends connected to the positive-electrode line Vcc1 of the auxiliary DC power supply E1 varies between a maximum value (E1+Vdc) and a minimum value E1 because the potential of the output terminal OUT varies between the common potential COM and the DC power supply potential Vdc.
Actually, however, a free wheel diode (not shown) is connected in parallel to each of the IGBTs 17, 18 in such a manner that its cathode is located on a collector side. Thus, when the free wheel diodes are in an ON-state, the potential of the output terminal OUT may have a negative value of several V relative to the common potential COM.
Next, operation of this level shift circuit will be described. The on signal 25 is applied to a gate of the MOSFET 1 to cause a current to flow through the MOSFET 1 to induce a voltage drop in the load resistor 3. When the potential at a lower end of the load resistor 3 becomes smaller than a threshold for the NOT circuit 8, an output from the NOT circuit 8 is set to the Hi level.
This Hi level is applied to a set terminal S of the RS latch 15 via the LPF 30 to set an output Q from the RS latch 15 to the Hi level, thereby turning the output IGBT 17 on via the driver 16. At the same time (strictly speaking, for prevention of a possible inter-arm short circuit, slightly before the point of turn-on), the IGBT 18 is turned off via a circuit (not shown) including the driver 20.
Next, the off signal 26 is applied to a gate of the MOSFET 2 to cause a current to flow through the MOSFET 2 to induce a voltage drop in the load resistor 4. When the potential at a lower end of the load resistor 4 becomes smaller than a threshold for the NOT circuit 9, an output from the NOT circuit 9 is set to the Hi level.
This Hi level is applied to a reset terminal R of the RS latch 15 via the LPF 31 to set the output Q from the RS latch 15 to a Lo level, thereby turning the output IGBT 17 off via the driver 16. At the same time (strictly speaking, for prevention of a possible inter-arm short circuit, slightly after the point of turn-off), the IGBT 18 is turned on via the circuit (not shown) including the driver 20.
When the output IGBT 18 is turned off or the IGBT 17 is turned on, this switching causes a rapid increase in potential dV/dt at the output terminal OUT to charge a capacitance between a source and a drain of each of the MOSFETs 1 and 2.
This charge current may induce a voltage drop in the load resistors 3 and 4 which is different from the true on and off signals, thereby causing the RS latch 15 to malfunction, mistakenly turning on the IGBT 17 to cause an inter-arm short circuit in the bridge circuit, or unnecessarily turning off the IGBT 17.
In addition to switching of the IGBTs 17, 18, extraneous noise may induce a similar abnormal voltage drop in the load resistors 3, 4.
The low-pass filters (LPF) 30 and 31 are inserted to prevent such malfunctioning of the RS latch 15 in order to remove, as abnormal signals, input signals of a small pulse width (a high frequency) resulting from switching or extraneous noise.
The reason why the on/off pulse signals 25, 26 are used to turn on and off the output IGBT 17 as in the circuit in FIG. 7 will be described below. In order to reduce harmonics components of an AC output from a PWM inverter or the like at low cost, it is desirable to increase a carrier frequency at which an output switching device is turned on and off and thus to operate the level shift circuit at a high speed.
To operate the level shift circuit at a high speed, a relatively high current must flow through the high-voltage MOSFETs 1, 2 for a level shift circuit. In particular, if a circuit section with a varying potential such as one shown by the broken line in FIG. 7 has a high potential, losses caused by the above current increase.
If, for example, a 10-mA current flows through the high-voltage MOSFET, the main DC power supply Vdc provides a voltage of 400 V, and the signal for turning on the high-voltage MOSFET is a signal that does not consist of pulses (in this case, only one MOSFET is used), then the average of losses on the high-voltage MOSFET occurring while the collector potential is high has a large value of about 2 W if the high-voltage MOSFET has an average on/off duty cycle of 50%.
Thus, the average loss on the high-voltage MOSFET is reduced by decomposing a current through the high-voltage MOSFET into pulses for turning the output IGBT on and pulses for turning the output IGBT off (in this case, two MOSFETs are used for turning the IGBT on and off) and minimizing the duration of these pulses.
Another reset input R of the RS latch 15 (the reset terminal 21 is connected to the RS latch 15) is used for resetting the RS latch 15 in an initial state or turning off the IGBT 17 when an error occurs.
If a level shift circuit such as one described above has high frequency signal components that may cause malfunctioning associated with dV/dt at the AC output terminal OUT, the components can be removed by the low-pass filters 30, 31. Low frequency components, however, are difficult to remove.
Consequently, with a large dV/dt, the time required by the AC output terminal OUT to reach the voltage VDC of the main DC power supply is short enough to prevent malfunctioning. With a small dV/dt, however, this time is long enough to cause malfunctioning.
To prevent this, the cutoff frequency of the low-pass filter can be reduced, but a problem of this method is that the reduction may increase a time delay in the level shift or require the width of on/off pulses to be increased, thereby increasing losses on the level shift circuit.
Another problem is that the value of a current resulting from on/off pulses must be increased due to the degraded constant-current characteristic of the high-voltage MOSFETs 1, 2 for the conventional level shift circuit. This will be described below.
FIG. 8 shows the relationship between the characteristics of a voltage VDS between a source and a drain (horizontal axis) of the high-voltage MOSFETs 1, 2 for a level shift circuit and the characteristics of a drain current ID (vertical axis) thereof, which is called the VDSxe2x88x92ID characteristic. This FIG. shows that the high-voltage MOSFET generally has a degraded constant-current characteristic due to resistance in a drift area (VDS maintains a large value until ID increases up to a constant value IH).
Accordingly, if the circuit section with a varying potential has a low potential, that is, the AC output terminal OUT has a potential close to the common potential COM [FIG. 8 shows a case where the terminal OUT has a potential equal to the common potential COM and where the power supply voltage for the load resistor circuit for the MOSFETs 1, 2 (that is, the voltage E1 of the power supply line Vcc1 with the load resistors 3, 4 connected thereto) is set equal to the voltage of the auxiliary DC power supply E1], a drain current IL flows which is determined by a load line 32 of the load resistor 3 or 4.
The load resistor 3 or 4 is set to have such a value as to sufficiently invert the output from the NOT circuit 8 or 9 due to a voltage drop caused by this current IL.
On the other hand, if the circuit section with a varying potential has a high potential, that is, the AC output terminal OUT has a potential close to the main-power-supply voltage Vdc [FIG. 8 shows a case where the terminal OUT has a potential equal to the main-power-supply voltage Vdc and where the voltage of the power supply line Vcc1 is set equal to (Vdc+E1)], a drain current IH flows which is determined by a load line 33 of the load resistor 3 or 4.
The drain current IH has a larger value than the current IL, thereby increasing losses on the level shift circuit.
It is thus an object of the present invention to provide a level shift circuit that meets a first object of preventing malfunctioning, regardless of the magnitude of dV/dt at the AC output terminal OUT, caused by switching of semiconductor switching devices in an inverter bridge circuit or by extraneous noise and without causing a time delay in the level shift circuit or increasing the width of on/off pulses, the level shift circuit also meeting a second object of preventing an increase on losses on the level circuit caused by the degraded constant-current characteristic of the high-voltage MOSFET.
To attain the above object, the present invention provides a level shift circuit comprising a first and a second controllable semiconductor devices each having an electrode acting as a potential reference and connected to a common potential, the potential reference electrode and a main electrode being electrically connected together while a conduction signal is being input between the potential reference electrode and a control electrode; a DC power supply having one electrode connected to an external circuit at a predetermined site varying between the common potential and a predetermined high potential and having a voltage lower than a voltage between the two potentials; a first and a second load resistors each having one end connected to the other electrode of the DC power supply and having the other end connected to the main electrode of a corresponding one of the first and second controllable semiconductor devices; and a logic circuit operating under the DC power supply, wherein a pulse-like conduction signal is input to each of the control electrodes of the first and second controllable semiconductor devices with different timings so that the conduction through the controllable semiconductor devices causes a pulse-like voltage drop in the first and second load resistors, the voltage drop being then communicated to the logic circuit as a signal.
The level shift circuit preferably includes signal-disabling means for preventing a signal corresponding to a pulse-like voltage drop from being communicated to the logic circuit when the voltage drop simultaneously occurs in the first and second load resistors.
In a further embodiment, the signal-disabling means masks a signal corresponding to a voltage drop in the first load resistor and communicated to the logic circuit, using a masking signal generated based on a voltage drop in the second load resistor, while masking a signal corresponding to a voltage drop in the second load resistor and communicated to the logic circuit, using a masking signal generated based on a voltage drop in the first load resistor.
In a further embodiment, the signal-disabling means uses thresholds for detecting a voltage drop in the load resistors to generate pulses in such a manner that a threshold for use in generating (via NOT circuits) pulses for the signal communicated to the logic circuit differs from a threshold for use in generating (via NOT circuits) pulses for the masking signal, in order to carry out the masking so that the pulse width of the masking signal entirely covers the pulse width of the signal communicated to the logic circuit.
In an additional embodiment, the signal-disabling means delays a front edge of a raw pulse signal generated by detecting a voltage drop in said load resistor, in order to obtain the signal communicated to the logic circuit, and wherein the signal-disabling means delays a rear edge of the raw pulse signal to obtain the masking signal in order to carry out the masking.
In a still further embodiment, the signal-disabling means carries out the masking in such a manner that no difference in generation exists between the signal communicated to the logic circuit and the masking signal and removes signals that remain despite the masking, via a low-pass filter.
In addition, the level shift circuit preferably comprises one or more sets of the controllable semiconductor devices and load resistors, a pulse-like conduction signal being input to each of the control electrodes of the controllable semiconductor devices wherein a current negative feedback resistor is inserted between the potential reference electrode of each controllable semiconductor device and common potential so that the voltage between the control electrode and the common potential has a predetermined value smaller than the voltage value of the DC power supply while each controllable semiconductor device is conductive.
Still further, the circuit includes constant-voltage diodes for limiting the voltage between the control electrode of each controllable semiconductor device and the common potential to the predetermined value.
Other advantanges and features of the invention will become apparent from the following detailed description of the preferred embodiments of the invention and the accompanying drawings.